(1) Field of the Invention
The invention relates to the integration of optical and electronic chips, and, more particularly, to a method to form a hybrid, VLSI-photonic integrated circuit using wafer bonding.
(2) Description of the Prior Art
In optical modules for access and metropolitan networking, several requirements are anticipated in the future. In particular, it is anticipated that transmitters, fibers, regenerators, switches, and receivers will become highly integrated components at distribution nodes. Very low cost, plug-and-play systems, such as transmitters and receivers, optical network units (ONU), and optical termination lines (OTL) optical network units (ONU), and optical termination lines (OTL) operating at frequencies in excess of 10 Gigabits/second will be required.
The current state of the art in heterogeneous integration is the silicon (Si) optical bench. On a silicon optical bench, various components, such as laser diodes, photodetectors, waveguides, and VLSI chips, are each picked, aligned, placed, and bonded onto a silicon substrate using flip chip technology and, more particularly, using solder bumps. These silicon bench modules thereby offer both optical signal and electrical signal processing functions on the same silicon substrate.
The optical performance of an optical transceiver is sensitive to the accuracy of the alignments between optical components such as between the fiber and the waveguide, between the waveguide and the laser, and between the waveguide and the photodetector. For example, in the reference by Kitagawa et al, “Hybrid Integration Technologies Using Planar Lightwave Circuits and Developed Components,” IEICE Trans. Electron., Vol. E85-C, No. 4, April 2002, p. 1009, it is found that the average optical signal loss for a single laser beam at a spot size converter to a planar waveguide interface is about 4.5 dB. Without the spot size converter, the loss increases to about 7 dB. In addition, it is found that silicon is a lossy substrate. For example, electrical interconnects, such as metal lines, become transmission lines at frequencies above 2 GHz. Further, such metal lines exhibit high propagation loss at frequencies above about 10 GigaHertz. As a notable application, optical transceivers, such as transimpedance amplifiers, clock data recovery circuits, multiplexers, and demultiplexers, have many clock and data lines running at or above 10 GHz. In such an application, the high propagation loss of the silicon substrate is a significant problem.
As for passive optical components, currently, silica-based materials, such as silicon oxynitride, silicon nitride, germanium-doped silicon oxide, or silicon-rich oxide, require high temperature annealing. For example, annealing at temperatures of greater than about 700° C. is required to form silica-based, passive optical components exhibiting low propagation loss of less than about 2 dB/cm as described in Worhoff et al, “Design, Tolerance Analysis, and Fabrication of Silicon Oxynitride Based Planar Optical Waveguides for Communication Devices,” Journal of Lightwave Technology, Vol. 17, No. 8, August 1999, p. 1401. The requirement for high temperature processing prevents monolithic integration of passive optical components with electronics chips. This high temperature processing effects transistor characteristics, increases contact resistance, and can melt metal interconnect layers.
Several prior art inventions relate to multiple substrate devices and optical devices. International Patent Application 02/48765 A1 to Pandraud et al and U.S. Patent Application 2002/0076130 A1 to Pandraud show methods to form features within substrates by bonding two substrates together. A waveguide structure with a reflective facet is shown. U.S. Patent Application 2003/0091264 A1 to Kimerling describes a hybrid device comprising an optical chip and an electronic chip. The two chips are bonded together using solder bumps. U.S. Pat. No. 6,455,398 B1 to Fonstad, Jr., et al discloses a method to form a hybrid integrated circuit device by bonding together a silicon wafer and a III-V semiconductor wafer, such as a GaAs wafer. Dielectric layers overlying the surfaces of each wafer are bonded together by a two step sequence comprising pressure and thermal processing. Embodiments describe thinning the silicon substrate such that a thin Si layer overlies then bonded dielectric layers which, in turn, overlie the III-V substrate. Electronics are formed in the Si layer and optoelectronics are formed in the III-V semiconductor layer. U.S. Pat. No. 6,456,767 B2 to Terashima shows an optical waveguide transmitter/receiver module. The module comprises a silicon substrate that is bonded together. The bonding surfaces are held together by resin, solder, or similar means. U.S. Application 2003/0140317 A1 to Brewer et al discloses various techniques for combining or for stacking substrates of differing composition. U.S. Patent Application 2003/0002809 A1 to Jian teaches an optical device where fibers are vertically integrated through the substrate layers. U.S. Pat. No. 6,020,624 to Wood et al describes a method to bond wafers together in a memory device. U.S. Patent Application 2002/0171077 to Chu et al teaches a silicon and silicon germanium optoelectronic integrated circuit.
Additional references related to the present invention include the article, by Akahori et al, “Assembly and Wiring Technologies on PLC Platforms for Low Cost and High Speed Applications,” Proceeding of ECTC, 1997, p. 632, and the article by Rieh et al, “Monolithically Integrated SiGe-Si PIN-HBT Front-End Photoreceivers,” IEEE Photonics Technology Letters, Vol. 10, No. 3, March 1998, p. 415. In addition, in the Bio-Opto Electronic Sensor Systems (BOSS) Center, a DARPA Optoelectronics Research Center, published on a web site: www.micro.uiuc.edu/boss/TaskII.html, the paper “Task II: Development of an Integrated Guided-Wave Interferometer-based Bio-Sensor System,” the relates to the topic of bio-sensors based on optical systems but does not disclose how to combine optical (III-V) wafers and silicon wafers.